1. Field of the Invention
The present invention relates to a data input/output circuit of a synchronous memory device and the method for controlling the same. In particular, the present invention relates to a bi-directional data input/output circuit of a synchronous memory device and the method for controlling the same in which a sequence control is rapidly executed when performing a write command during a read operation in the case where read data and write data are transmitted on a single data line.
2. Description of the Prior Art
A data input/output circuit of a conventional synchronous memory device includes a data bus sense amplifier and a write data driver which are associated with data paths in a block, and a data input buffer and a data output buffer which are associated with an input/output operation of the entire data. Wirings, which transfer data signals between these circuits, that is block data-related circuits and global data-related circuits, are called data bus lines.
The prerequisite issues in designing these data bus lines involve the following methods: first, whether or not the data input/output lines will be wired individually or whether or not they will be used as a common line (bi-directional bus); second, in each of the above cases, whether or not high potential data and low potential data will be both transferred through a single data line (single-ended data bus method), or whether or not the data line for transmitting a single data will be implemented as two data lines so that one of the two data lines is used to transmit only a high potential signal and the one of the two data lines is used to transmit only a low potential signal (double-ended data bus method).
With respect to the above second method, an explanation will be given in more detail as follows. Typically, digital data becomes binary data; a high potential and a low potential. In other words, it determines whether or not to transmit the data on a single line simultaneously, that is, to transmit both the high potential and low potential on a single driving line simultaneously, or otherwise with a high potential-dedicated line and a low potential-dedicated line installed therein where the two lines are initialized to become an initial high potential (or initial low potential), or it determines whether or not to make the high potential-dedicated line become a low potential (or high potential) when transmitting the high potential and to make the low potential-dedicated line become a low potential (or high potential) when transmitting the low potential. The second decision is advantageous in a high speed operation but has a disadvantage in that it requires a lot of area for wiring data lines.
FIG. 1 shows a block structure of a bi-directional data input/output circuit of a synchronous memory device showing data paths in accordance with a conventional method. In FIG. 1, a block read data outputted from a memory device drives an input/output data bus line 101 through a data bus sense amplifier (db-sense amp. 102). Then, the data on the bus line is outputted to outside the memory device through a data output buffer 103 being a global read data receive section. Also, the data written from the outside of the memory device to the inside thereof drives an input/output data bus line 101 through a data input buffer 105 being a global write data driver. This is inputted to the internal of the memory device through an internal input buffer 104 within the memory device being a block data receive section.
A post charge logic 106 acts to recharge and then initialize the data line through a CMOS switching circuit, wherein a switching control signal is consisted to delay and generate a potential shift of the data line through a delay circuit.
However, in the data input/output circuit constructed as above, when a read operation and a write operation are performed, that is, the operations which begin at one clock in the read operation of a synchronous memory device may not be finished before a next clock signal is received, but there are cases where the operation is performed on more than one clock.
In this case, the time when the data signal generated by the read operation is carried onto a commonly used data line becomes the time after a next clock is received after the read command is received. Then, if commands in continually received next clocks are written thereto, the data signal inputted simultaneously with the write command will be rapidly carried onto the data line.
Accordingly, two data signals, that is, the data signal generated by the read operation and the write data signal for a write operation will be carried onto it simultaneously, thereby causing an erroneous operation. This phenomenon is more serious when the clock period is high.
In order to prevent such an erroneous operation, solutions are provided which limit the operation of the memory device to perform the write operation after the read operation is completely finished, or uses the data line used upon a read operation and the data line used upon a write operation, individually. However, the former sacrifices the speed in switching between the read operation and the write operation and the latter has a disadvantage in that it takes a lot of a chip area.
FIG. 2 is a drawing for explaining a minimum clock period for the bi-directional data input/output circuit of a synchronous memory device shown in FIG. 1. Referring to FIG. 2, in order for the continuous read-write operation to be properly operated, when the write command is performed in a next clock clkt2 during when the read operation is performed in clkt1, the conditions in which any erroneous operation is caused in a conventional circuit are as follows:
tclk+t3&gt;t1+t2 PA1 That is, tclk&gt;t1+t2-t3
(where, t1 indicates the time when the data signal generated upon the read operation is carried onto the data line, t1 indicates the pulse width of the data line, and t3 indicates the time when the data signal generated upon the write operation is carried onto the data line)
In other words, the continuous clock periods of the memory device are limited to the time called t1+t2-t3. More particularly, it is limited to one for t2 region to which current read data are being transmitted.